Embodiments of the present disclosure generally relate to a semiconductor test device and a semiconductor test method, and more particularly to a semiconductor test device and a semiconductor test method applying different test commands to a plurality of semiconductor chips contained in a wafer when testing the wafer.
Semiconductor device testing is a process to make sure whether a semiconductor device (e.g., DRAM and flash memory) functions as intended. Wafer testing is a process performed during semiconductor device fabrication, and, during the wafer testing process, the semiconductor devices in a wafer may be tested by a semiconductor test device.
Since the semiconductor test device is generally very expensive, the wafer testing is performed by using a limited number of semiconductor test devices. Higher levels of integration on a semiconductor device lead to significant increase in test time. As the test time is increased, the entire manufacturing process, from a wafer to packaged semiconductor chips, takes more time than before. Therefore, there is a need to test as many semiconductor chips as possible at the same time by using a single semiconductor test device.
During the wafer testing, the semiconductor test device is connected to a limited number of pins of each semiconductor chip, and the semiconductor test device usually applies the same signal to all the semiconductor chips of the wafer to reduce the number of pins needed for the wafer testing. Accordingly, address pins of respective semiconductor chips may receive the same signal from the semiconductor test device.
Under this testing environment, even in a situation where different test commands need to be applied to respective semiconductor chips, if a test command is applied to the semiconductor chips through the address pins, the same test command is applied to all the semiconductor chips. In addition, under this testing environment, if the respective semiconductor chips use different pins in receiving the test command, the semiconductor test device will need to have as many terminals as possible, and it will be difficult to apply different test signals to the respective semiconductor chips.